? semiconductor components industries, llc, 2010 july, 2010 ? rev. 1 1 publication order number: PCS3PS550A/d PCS3PS550A general purpose peak emi reduction ic product description the PCS3PS550A is a versatile 2.3 v to 3.6 v, timing ? safe ? , spectrum frequency modulator designed specifically for a wide range of clock frequencies. the PCS3PS550A reduces electromagnetic interference (emi) at the clock source, allowing system wide reduction of emi of all clock dependent signals. the PCS3PS550A allows significant system cost savings by reducing the number of circuit board layers ferrite beads, shielding that are traditionally required to pass emi regulations. features ? lvcmos peak emi reduction ic ? input clock frequency: 18 mhz ? 36 mhz ? output clock frequency: 18 mhz ? 36 mhz ? eight different selectable spread options ? power down option for power save ? supply voltage: 2.3 v ? 3.6 v ? 8 ? pin wdfn , 2 mm x 2 mm (tdfn) package ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? the PCS3PS550A is targeted towards consumer electronic applications. wdfn8 case 511aq marking diagrams http://onsemi.com pin configuration see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information sr2 sr1 sr0 pd# vss modout clkin PCS3PS550A vdd 1 cam 1 ca = specific device code m = date code = pb ? free device 1 2 3 4 8 7 6 5
PCS3PS550A http://onsemi.com 2 vss vdd clkin modout pll sr0 sr1 sr2 pd# figure 1. block diagram PCS3PS550A modulates the output of a single pll in order to ?spread? the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. this results in significantly lower system emi compared to the typical narrow band signal produced by oscillators and most frequency generators. lowering emi by increasing a signal?s bandwidth is called ?spread spectrum clock generation?. PCS3PS550A accepts an input from an external reference clock and locks to a 1x modulated clock output. sr0, sr1 and sr2 pins enable selecting one of the eight different frequency deviations (refer frequency deviation selection table). PCS3PS550A also features power down option for power save. PCS3PS550A operates over a supply voltage range of 2.3 v to 3.6 v. PCS3PS550A is available in an 8 pin wdfn, (2 mm x 2 mm) package. table 1. pin description pin# pin name type description 1 clkin i external reference clock input. 2 sr2 i digital logic input used to select spreading range. there is no default state. refer frequency deviation selection table. 3 pd# i power ? down control pin. powers down the entire chip. there is no default state. pull low to enable power ? down mode. connect to vdd to disable power down. output clock will be low when power down is enabled 4 vss p ground connection. 5 modout o spread spectrum clock output. 6 sr1 i digital logic input used to select spreading range. this pin has an internal pull ? up resistor. refer modulation selection table. 7 sr0 i digital logic input used to select spreading range. there is no default state. refer frequency deviation selection table. 8 vdd p power supply for the entire chip
PCS3PS550A http://onsemi.com 3 table 2. frequency deviation selection table sr2 sr1 sr0 spreading range ( %) (@ 24 mhz) 0 0 0 1 0 0 1 2.5 0 1 0 1.25 0 1 1 1.5 1 0 0 0.4 1 0 1 0.75 1 1 0 1.75 1 1 1 2 table 3. operating conditions symbol parameter min max unit v dd supply voltage with respect to v ss 2.3 3.6 v t a operating temperature ? 20 +85 c c l load capacitance 15 pf c in input capacitance 7 pf table 4. absolute maximum rating symbol parameter rating unit v dd , v in voltage on any input pin with respect to vss ? 0.5 to +4.6 v t stg storage temperature ? 65 to +125 c t a operating temperature ? 40 to +85 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22 ? a114 ? b) 2 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability.
PCS3PS550A http://onsemi.com 4 table 5. dc electrical characteristics symbol parameter min typ max unit v dd supply voltage with respect to v ss 2.3 2.8 3.6 v v ih input high voltage 0.65 * v dd v v il input low voltage 0.3 * v dd v i ih input high current (sr1 control pin) 50 a i il input low current (sr1 control pin) 50 a v oh output high voltage (i oh = ? 8 ma) 0.75 * v dd v v ol output low voltage (i ol = 8 ma) 0.2 * v dd v i cc static supply current (pd# pulled to v ss ) 1 a i dd dynamic supply current (unloaded output @ 24 mhz) 6 9 ma z out output impedance 40 table 6. ac electrical characteristics symbol parameter min typ max unit clkin input clock frequency 18 24 36 mhz modout output clock frequency 18 24 36 mhz t lh (note 1) output rise time (measured between 20% to 80%) unloaded output 0.8 1.2 ns cl = 15 pf 2.4 3 t hl (note 1) output fall time (measured between 80% to 20%) unloaded output 0.6 1 ns cl = 15 pf 1.9 2.8 t jc (note 1) jitter (cycle to cycle) unloaded output 175 250 ps t d (note 1) output duty cycle 45 50 55 % t on (note 1) pll lock time (stable power supply, valid clock presented on clkin pin, pd# toggled from low to high) 3 ms fd var frequency deviation variation across pvt 2.5 5 % 1. parameter is guaranteed by design and characterization. not 100% tested in production
PCS3PS550A http://onsemi.com 5 note: refer pin description table for functionality details. clkin vss vdd 2.2 f c2 modout modout clock PCS3PS550A sr2, sr1, sr0 frequency deviation selection control vdd 0 0 0.1 f m clock r rs 0 0 vdd pd# c1 sr2/sr1/sr0 power down control vddin figure 2. typical application schematic 1 2,6,7 5 3 8 4 pcb layout recommendation for optimum device performance, following guidelines are recommended. ? dedicated v dd and gnd planes. ? the device must be isolated from system power supply noise. a 0.1 f and a 2.2 f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between the decoupling capacitor and vdd pin. the pcb trace to vdd pin and the ground via should be kept as short as possible. all the vdd pins should have decoupling capacitors. ? in an optimum layout all components are on the same side of the board, minimizing vias through other signal layers. a typical layout is shown in the figure as short as possible vdd gnd clkin pd# sr0 sr2 modout vss sr1 as short as possible r rs figure 3.
PCS3PS550A http://onsemi.com 6 ordering information part number top marking temperature package type shipping ? PCS3PS550Ag ? 08cr ca ? 20 c to +85 c 8l ? wdfn(tdfn) (pb ? free) tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *a ?microdot? placed at the end of last row of marking or just below the last row toward the center of package indicates pb ? free.
PCS3PS550A http://onsemi.com 7 package dimensions wdfn8 2x2, 0.5p case 511aq ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal. c a seating plane d e 0.10 c a3 a a1 0.10 c dim a min millimeters 0.70 a1 0.00 a3 0.20 ref b 0.20 d 2.00 bsc e 2.00 bsc e 0.50 bsc pin one reference 0.05 c 0.05 c 8x a 0.10 c note 3 l e b b 4 5 8x 1 8 0.05 c 0.50 l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.30 0.50 0.78 7x dimensions: millimeters bottom view 0.35 pitch 8x 0.80 0.05 0.30 0.60 max l1 detail a l optional constructions l --- l1 0.15 b top view side view e/2 1 package outline detail b detail a 2x 2x 8x recommended 0.88 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 PCS3PS550A/d timing ? safe is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
